Mock Tapeout
Learn chip tapeout on real boards, in a week, for tens of euros.
A first chip tapeout is slow and expensive, and once the silicon is back nothing inside it can be seen. Mock Tapeout is an open virtual fab: your RTL goes through the same steps as a chip (synthesis, placement, routing, DRC, LVS, timing signoff), but the "die" is a printed circuit board and the standard cells are ordinary logic ICs.
Boards come back in about a week, a failed design costs
tens of euros to redo, not another shuttle, and every internal net can be probed with a
logic analyser.
The fab, mapped onto boards
| Real tapeout | Mock tapeout |
|---|---|
| Standard-cell library | Single-gate logic ICs, plus counters, adders and decoders |
| Liberty timing | Datasheet delays, load dependent |
| Metal stack and design rules | PCB layers and manufacturer rules |
| DRC, LVS, extraction, STA | The same checks, on copper |
| Multi-project wafer shuttle | Many student designs on one panel |
| 3D stacking | Stacked boards joined by pin headers |
| Wafer tester | A carrier board that runs test vectors |
Who it is for
- Students and teachers of digital and VLSI design who want a hands-on tapeout lab.
- Anyone preparing a first silicon design for an open shuttle such as Tiny Tapeout, who wants to practise the flow first.
- Makers who build logic-chip computers and want a real design flow behind them.
Status
Mock Tapeout is in early development. The PDK, the flow and the course material will be released under free licences. If you teach a course and would like to run a pilot shuttle, or just want to hear when the first shuttle opens, write to serge@rabyking.com.